Expression unsynthesizable

i have a simple mux expression in my code, but synthesis says it’s unsynthesizable. it appears it doesn’t like the 1.5 in the expression. can i use 3/2, which appears to work? how do i get it to accept 1.5?

parameter para = 10;
parameter parb = 20;

assign z = x ? (y ? (para3 - 1) : (parb1.5 - 1)) : 0;

[QUOTE=deadspace;1886]i have a simple mux expression in my code, but synthesis says it’s unsynthesizable. it appears it doesn’t like the 1.5 in the expression. can i use 3/2, which appears to work? how do i get it to accept 1.5?

parameter para = 10;
parameter parb = 20;

assign z = x ? (y ? (para3 - 1) : (parb1.5 - 1)) : 0;[/QUOTE]

Reals aren’t supported in this context in verilog.
It all has to resolve to an integer/bit array that can be stuffed into the types
of y and x.

Why do you want it to be 1.5, and not 3/2?

alan