Downloading bit files using ISE (Webpack 9.2i)

Xilinx FPGA
1

Dear Sirs,
I am using an XEM3005 card placed on an BRK3005 breaker board. I have managed to download your examples (e.g. counter) using FrontPanel, but when I try to compile the

counters.vhd
xem3005.ucf

using ISE Webpack 9.2i

I get the following errors:
ERROR:NgdBuild:604 - logical block ‘ep00’ with type ‘okWireIn’ could not be

ERROR:NgdBuild:604 - logical block ‘ep20’ with type ‘okWireOut’ could not be

ERROR:NgdBuild:604 - logical block ‘ep21’ with type ‘okWireOut’ could not be

ERROR:NgdBuild:604 - logical block ‘ep40’ with type ‘okTriggerIn’ could not be

ERROR:NgdBuild:604 - logical block ‘ep60’ with type ‘okTriggerOut’ could not be

ERROR:NgdBuild:604 - logical block ‘ep61’ with type ‘okTriggerOut’ could not be

ERROR:NgdBuild:604 - logical block ‘okHI/hicore’ with type ‘okHostInterfaceCore’

I have found the corresponding ngc files, but cannot seem to compile the whole project. Are these libraries needed if one wants to simply download using a JTAG cable (USB used only for power). Could you provide a step by step walkthrough for downloading one’s project?

Thank you in advance,
Demosthenes Doumenis

2

Please refer to the FrontPanel User’s Manual (p. 32 of the current version):

— Begin quote from ____

You should also copy the pre-synthesized files (*.ngc) that you use into your project directory. You won’t need to copy module files that you are not using. The .ngc files will then be used by the Xilinx tools during the Translate step in order to completely build the FPGA configuration file.

— End quote

Did you do this step?

These libraries are required for any design that makes use of the Opal Kelly FrontPanel HDL modules, regardless of how you download the bitfile.

The Getting Started Guide that was printed and included in your package contains the “walk-through” that you are referring to. If you need more of a tutorial, please see our online Tutorial through the “Support” page:

http://wiki.opalkelly.com/tutorial