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Asynchronous FIFO generate
[
Spartan-6 USB 3.0 Modules
]
(
1
)
VHDL ramtest XEM3010
[
Contributions
]
(
12
)
XEM7010-A50 ISE support?
[
Xilinx 7-Series
]
(
12
)
Error loading libcpprest.so.2.8 when running FrontPanel
[
FrontPanel
]
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2
)
XEM6310 sometimes stuck
[
Spartan-6 USB 3.0 Modules
]
(
3
)
Trouble moving from ISE to Vivado
[
Xilinx 7-Series
]
(
3
)
Transferring Data using Verilog and Python
[
VHDL / Verilog Discussion
]
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2
)
Data acquisition from a TI 100MSPS ADC via HSMC
[
Cyclone IV USB 3.0 Modules
]
(
1
)
Running Pipetest but Front Panel DLL not load
[
FrontPanel
]
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2
)
BTPipeout issue (XEM6310)
[
Spartan-6 USB 3.0 Modules
]
(
2
)
FPGA configuration failed: Cannot find configuration file
[
FrontPanel
]
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4
)
Compiling C++ project with CMake and FrontPanel
[
FrontPanel
]
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1
)
Congrats for the new FOMD-ACV
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uncategorized
]
(
2
)
FrontPanel and Python
[
FrontPanel
]
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2
)
Write and read on ddr2 sdram for xem6010-lx45
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Spartan-6 USB 2.0 Modules
]
(
2
)
FrontPanel 3.0.11 labview palette
[
FrontPanel
]
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18
)
Any example for a simple ADC interface?
[
uncategorized
]
(
2
)
OK HDL to Serial Peripheral
[
Xilinx 7-Series
]
(
1
)
Create FrontPanel use C++
[
FrontPanel
]
(
3
)
Problem Loading okFrontPanel Library into MATLAB using 64 bit system
[
FrontPanel
]
(
1
)
LVDS and SLVS on XEM6310
[
Spartan-6 USB 3.0 Modules
]
(
5
)
Xem7350 ddr mig
[
Xilinx 7-Series
]
(
1
)
Okpipeout with C#
[
FrontPanel
]
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5
)
Programming System Flash on Altera-based boards
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uncategorized
]
(
3
)
ReadFromBTPipeOut timeout?
[
FrontPanel
]
(
6
)
LabVIEW VI's Not Executable When Importing FrontPanel DLL
[
FrontPanel
]
(
2
)
Creating a forum to discuss Vivado/AXI with OK HDL endpoint development
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Suggestions
]
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5
)
What File need for using XEM-3005 Board
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uncategorized
]
(
3
)
XEM6310 RAMTester problem!
[
Spartan-6 USB 3.0 Modules
]
(
8
)
Front Panel Python API with non-system python on Mac
[
FrontPanel
]
(
2
)
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