I am looking for passive and active headsink recommendations for the Virtex5. It gets hot. I used the RAMtester code as a baseline as it is similar in to one of your end applications. A passive low profile heatsink is not sufficient. Can you please a recommendation that will adhere to the...
I am getting a compile error when attempting to compile RAMTester.cpp. The compile returns: g++ -fPIC -DLINUX -c RAMTester.cpp RAMTester.cpp: In function ?int main(int, char**)?: RAMTester.cpp:216: error: ?srand? was not declared in this scope make: *** Error 1 Does the Makefile need to...
From the xem5010.ucf file: NET "xbusp<3>" LOC = "G25"; # JP2_9 **** NET "xbusn<3>" LOC = "G24"; # JP2_11 **** NET "xbusp<4>" LOC = "J26"; # JP2_10 **** NET "xbusn<4>" LOC = "J25"; # JP2_12 **** From the User's Manual: 9 G24 L3P_SM5P_13 11 G25 ...
How do I find out the speed grade of the Virtex-5 FPGA?
Hi sir, I'm using XEM5010. I tested the board with the RAMTester-xem5010.bit .(renamed to ramtest.bit) But it doesn't work at all!! And I have 2 5010 boards and the test results are same.
I found a mistake on the BRK5010 breakout board. Signals from the XEM5010 JP2 pins 90 and 92 (FPGA pins AE26 and AD26) did not get routed to header JP2C on the breakout board. The remaining even numbered signals on JP2 pins 94-108 were routed to JP2C pins 90-104 (in other words, they were shifted...
In the XEM5010 UG, on pages 20-23. In the FPGA LVDS column. They are labelled with notations, that I am unable to cross reference with the vertex5lx UG. Can you tell me what the following in those columns means: SMxP/N, where x goes from 0 to 8. CC GS CC_GS
Can anyone assist/comment on using System Monitor with the 5010? Since we don't have access to schematics, it is NOT clear how (if at all) the required A/D pins are connected (VREF, VP, VN, etc.). In Chipscope I get NO valid values for temp or voltages. There is no mention of System Monitor...
Administrator: Thanks for setting up this forum space. I am looking for a SSRAM verilog model for the GSI GS8322Z36-200V part or equivalent. As commented on to my question regarding DDR2 access, the access model for the SSRAM is much simpler, but would like the confidence that I am correctly...
I am trying to reconcile the RAMtester example simulation results with the timing diagrams found in the MIG user guide. I have the following questions: Are the addresses specified by app_af_addr word vs byte addresses? The simulation increments the address by 4, which if byte address is on...
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