Forum: Xilinx FPGA

hello.. I need to design the serial eeprom (AT24C256W) controller which will read and data to/from fpga.i m using sparten3 xc3s2000 fpga board. can anyone help or give some example.. waiting... regards

Hi, is it possible to create a subsystem in schematic then save it in my library?And how do them? Thank you.

Hi, I would like to perform my own memory using LUTs with one input in ise in schematic.When I make test for one LUT in modelsim I always have 0 at the output whatever the bit at the input.What should I do to get the same bit in the input and output of LUT? How do I connect LUTs to obtain a...

Hi everyone. I am new to Opal Kelly. I want to simulate the First.v file that is in samples. I didn't change neither First.v nor First_tf.v. I copied .ngc files and okLibrary.v to project folder. I added these lines to modelsim.ini file okFPsim_ver = C:/Program Files/Opal...

Hi, i am using xilinx edk 10.1.02. i have a verilog memory model of issi asynchronous sram found on xilinx spartan 3 board. how can i 1)simulate the model with microblaze using edk?wat is the procedure to be precise? 2)secondly as it is an asynchronous sram model do i need an...

Hi,I work with virtex 4(VHDL) and i want to implement a processor miniMIPS and i find an information that says:"The miniMIPS was integrated in an FPGA from Xilinx Xc2V1000-5fg456" but i can't find find haw to do this;does anyone can help me and give me a tutorial and datasheet of this...

Hi All, I'm new to FPGAs and need some help in indentifying an FPGA for our project. The requirements are - fit ~500K ASIC gates - two DDR1/2 interfaces -> how does the memory control work? Do I need to port a controller or is in-built into the FPGA - one USB2.0 interface ->...

Hi all. I was wondering is there any way to see number of flip flops per module after synthesis and implementation in Xilinx ISE? I see different parameters on module level utilization like number of LUTs. SLICEs, LUT RAM, etc. I checked every report but I can't find it anywhere. :confused: It's a...

Hi All I'm implementing an IEEE 802.11 protocol on FPGA. The FPGA is connected to some external sensor which emasuring temprature and some othe parameters and will transmit(wirelessly) to other modules which are same as the transmitter( FPGA borad and external sensors). The problem is I have...

Hi. In my design I have some verilog modules that are "empty", that is they contain only port declaration and no instances or assign statements. I want to keep them this way and change them later. Is there any way to run complete synthesis and implementation with this kind of modules? I declared...

I would like to know if the memory controller generated by Xilinx (using the Xilinx MIG) can be used on the Opal Kelly board. I would like to know the pros and cons of using the Xilinx generated memory controller vs the memory controller provided by Opal Kelly? Would the design of a memory...

Hi , I want to use ? XC2S150PQ208? . I want to convert it from SMD to THD (for easily use), now I have much space under it . can I design an EEProm(XC18V04) under chip ? thanks for your attention

Hello everybody. I'm studying the viability of using pattern matching on an FPGA. My VHDL code runs ok in Simulation: it takes characters from a file. I need to execute this into an FPGA and communicating with the PowerPC, but I don't know how to take characaters from the file. Anyone can help...

I am having problems generating program files in Xilinx WebPACK 10.1. The program files I generate do not work when I load them into the FPGA using FrontPanel. My setup is as follows: Ubuntu 8.04 Xilinx XEM3001v2 with f/w 3.0 FrontPanel-3.0-FC5 (the FC7 version would not work with Ubuntu...

Okay, I am just starting to program in verilog and I don't understand this error at all. Can you help me? Here is code: module testingIf(in, out); input in; output out; reg x;

When I installed the Front Panel software on a new computer from the CD I got with an XEM3001 I purchased in march 2008 I realized there are two versions of the host interface vhdl (okLibrary.vhd): One in C:\Program Files\Opal Kelly\FrontPanel\XEM3001v2\Xilinx the other in C:\Program Files\Opal...

Dear Sirs, I am using an XEM3005 card placed on an BRK3005 breaker board. I have managed to download your examples (e.g. counter) using FrontPanel, but when I try to compile the counters.vhd xem3005.ucf using ISE Webpack 9.2i I get the following errors: ERROR:NgdBuild:604 - logical...

can anyone help me what tools should i get so that i can synthesize my VHDL coding, do a functional simulation and do pin assignment. I'm not familiar with xilinx tools because i only know how to use quartus. Help me:(

Hello, I have serious "time" problem!!! I need your help about a project for PicoBlaze. in this project i have firstly to write assembly code/program for picoblaze describing a kind of fire alarm system which then i will use it in Xilinx ISE 9.2 program into an older program/system as a...