Forum: XEM3010 - Spartan-3 Integration Module

Hi, I need a pointer in diagnosing a problem I have in using the IsTriggered function of the Matlab API. I built a data acquisition application with XEM3010. The FPGA on XEM controls a bunch of hi-speed ADCs on a carrier board. It works like this, each time when my Matlab application sends a...

I am having a problem with reading from the FIFO's using pipes. My FIFO's 2048 big and 16 wide and I am writing to it at about 100 MHz. The problem is that the computer is not reading from the FIFO fast enough at its speed of 48 MHz to remove the bytes from the FIFO and make space for the...

hi there, I am a newbie in Frontpanel and recently I am working on XEM3010 to make Frontpanel working. From your Frontpanel datasheet, it mentioned that the element "bit" of okCombobox is the bit number to which this component addresses. I don't understand how it works, as one bit only can...

Hi, In samples "Ramtester" and "DEStester", we have different formats of SetWireInValue function such as dev->SetWireInValue(0x00, 0x0002); (In "Ramtester") and xem->SetWireInValue(0x10, 0xff, 0x01); (In "DEStester") They have different number of parameters. Could you please explain why? Thanks!

I am designing an interface board to the XEM3010 and want to bring in a high speed LVDS clock from a clock generator to the XCLK LVDS input. now the user manual states that the Vcco for bank 1 is set to 3.3V but it is ok for differental inputs because it uses Vccaux instead of Vcco. my question is...

I'm trying to obtain the raw pinouts for the XEM3010 Spartan FPGA. I know that pins are specified in the XEM3010 User Manual, but I didn't see the pinouts for the USB controller or the Cypress PLL chip, for example.

hi, the power led of my 3010 is flickering. the 1.2 V output seems fine, but the 3.3 V output is oscillating at about 18 Hz with a duty cycle of 30% between 0 and 3.3 V. it looks like the 3.3 V regulator is gone. any recommendations for replacing or figuring out if that is indeed the case or if...

Hello, Is it possible to implement a JTAG connection in verilog/vhdl to the expansion pins on the breakout board for the XEM3010. I saw that JTAG connections already existed on JP1; however, I wanted to send data from the FPGA to another device, using a JTAG connection.

Hello, I am planning to purchase XEM3010 (and maybe XEM5010 after some time) but I have a question about the SAMTEC connector on XEM3010. I have to route the signals on the SAMTEC connector onto a connector such as a screw-terminal. I'm looking for a solution but so far unable to find one. Is...

help me, please, it's too important and urgent. I have to built an API with labview for a card developed by but I have'n found nobody knows how your labview's library work. I followed your suggestions but it doesn't work and I don't know what I'm not doing. The okusbfrontpanel_construct...

Hi, I've done an application for XEM3010 with Labview 8.5, I'm using your kUSBFrontPanel components for Labview but I get this error LabVIEW: An exception occurred within the external code called by a Call Library Function Node. The exception may have corrupted LabVIEW's memory. Save any work...

I have a multithreaded application that relies on controlling the configuration of the FPGA through okWireIn endpoints, and records the results from the okBTPipeOut. The program works, but i have found that the BTPipeOut doesn't timeout, even when i set the Timeout value to be very small...

How should I transfer the PROM programming file to the PROM? there are several possibilities or should I use a JTAG cable? I haven't been able to find a proper cable to buy on the Opal-Kelly web-site. Is this the right cable: Xilinx Platform Cable USB (for JTAG Hardware Debug connection)? how...

I'm trying to get the Counters sample project up and simulating in ModelSim XE 6.3c. I have done the following: * Created a new VHDL project in Xilinx Project Navigator v10.1.03 * Copied okLibrary.vhd, Counters.vhd & xem3010.ucf from the Samples dir to the project dir * Created...

Using ISE 9.2.04i with ModelSim 6.2g. Added path to Modelsim.ini with changes to point to ModelSimXE62g. Lunching Modelsim from ISE. Test bench is modified dut_tf.vhd. Tried also using custom do for the properties for ModelSim in ISE. Also tried lunching ModelSim outside of ISE and executed the...

Hi, I wanna communicate the FPGA with the PC by LabVIEW but I have a problem, I don't know how begin. Please help me:confused:

O-K tech support, Could you be so kind to provide me with the source and PN for the inductor L2 on XEM 3010 ? The case of L2 on my development board cracked up, probably due to heat. The board is still working, but I would like to replace it just for a piece of mind. Thanks. mahengjie:)

i have make a new project for datalogging,and it works well.now,i add a okTriggerOut module,but translate can't pass. error message show that all 'ok2' have problem, like that: ERROR:NgdBuild:456 - logical net 'ok2<8>' has both active and tristate drivers... Active driver(s) of net...