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View Full Version : XEM3010 - Spartan-3 Integration Module

  1. NGC files for XEM 3010-1500P Board
  2. BRK3010 Protel 2004 Project
  3. VHDL Memory Controller
  4. Pads Library for XEM3010
  5. HDL libraries for ISE 8
  6. RAMTest DLL Port - Cant make it work
  7. Power Supply for XEM3010-1500P
  8. VHDL SDRAM Controller
  9. Simulation support for ncsim
  10. Interfacing XEM3010 and Linux
  11. Ramb16_s18_s18 core
  12. Connecting WireIn & WireOut together
  13. SDRAM Controller
  14. XEM3010 availability
  15. SDRAM Clock
  16. Verilog for okLibrary modules
  17. Buffered Pipe In problem
  18. okBufferedPipeIn / okBufferedPipeOut problem
  19. Reset on XEM-3010-1500P?
  20. How to access sofware downloads
  21. I2C From FrontPanel
  22. sdram manufactorer and part number
  23. FrontPanel and MicroBlaze
  24. RAMTester Bitfiles
  25. Requesting inforamtion regarding ti_clk / hi_clk
  26. first.v P&R error with 3010:ERROR:NgdBuild:604
  27. ncverilog support
  28. P&R in xps 7.1 NGDBUILD ERROR
  29. Unstable readings from WireOuts - take 2
  30. Can the FIFO size be increased?
  31. writng C driver for spartan board
  32. No Signals on BRK3010
  33. No affect on PLL
  34. VB6 and okFrontPanel.dll
  35. How to set PLL for SDRAM?
  36. Write to XEM3010
  37. JTAG connection question
  38. Pinout of BRK3010
  39. I/O defaults
  40. MicroBlaze updated to EDK 8.2.2
  41. Problem DLing software updates
  42. USB communication error
  43. Change VID/PID on XEM3010
  44. Fifo Interface
  45. TBUF with black boxes
  46. Where to find the Linux distribution files?
  47. XEM3010: Layout of pins for LVDS/differential signals
  48. Deallocation error
  49. Access to differential termination for XCLK1/2
  50. UCF constrains for XEM3010
  51. FP v3.0.1 Which firmware is required?
  52. Pinout Mappings FP 1.x to FP 3.0
  53. FIFO for okBTPipeOut versus the old okBufferedPipeOut
  54. Issues downloading bit file.Getting okFILE_ERROR
  55. SDRam Controller under FP-3
  56. Connecting USB through JP2/3 ?
  57. Issues with ReadFromPipeOut
  58. Sdram
  59. Achieving perfect match between the XEM3010 and its motherboard
  60. DESTester example with Visual C++ 2005
  61. DESTester example with Visual C++ 2005
  62. GCLK IOB Standard
  63. segmentation error
  64. My XEM-3010 is not working
  65. RAMTester & PipeTest fail
  66. Can one determine the PIPEIN word count on the FPGA side with VHDL/Verilog?
  67. Cannot reprogram XEM3010
  68. oscillator stability
  69. Trying to build the wxWidgets Solution
  70. Programming the Xilinx PROM
  71. Booting from PROM
  72. XEM3010 with ethernet
  73. Problem with okUsbFrontPanel_ReadI2C
  74. Vsim-3173 Entity work.okhostinterfacecore has nor architecture
  75. problems with sdram
  76. Bom & Coo?
  77. LVDS Spartan3 VHDL
  78. how to use Xilinx PROM from Microblaze on XEM3010-1500P
  79. How to generate *.bit file by myself?
  80. How to simulate the sample of RAMTester under ModelSim 6.1a?
  81. signal/pin assignment
  82. How does the "rowaddr" work in sample "RAMTest"?
  83. How to supply power to an LVDS clock?
  84. ReadFromPipeOut errors
  85. meaning of S/N
  86. New to OK- Unable to Translate First.v
  87. Matlab API problem: IsTriggered function seizing ?