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View Full Version : XEM3001 - Spartan-3 Integration Module

  1. Welcome!
  2. Maximum tested throughput?
  3. Beginner help with WebPack
  4. Linux drivers available?
  5. XEM3001 / FrontPanel Tutorial Available
  6. Plead for help
  7. Memory size question
  8. Starting with HDL
  9. Windows driver
  10. USB module for DSP
  11. XEM3001 questions
  12. Accessing from Virtual PC on a Mac
  13. XEM3001 Out of Stock
  14. FPGA to USB protocol
  15. XEM3001 Spartan 3 speed rating
  16. differential output
  17. New versions of XEM
  18. New XEM3001 have arrivede .
  19. Power availability
  20. Basic Register I/O to Module
  21. XEM3001 firmware
  22. FPGA become hot!
  23. Is the I2C master controller available?
  24. Compiling counters vhdl
  25. Problems downloading a configuration file
  26. Mechanical Drawing for the Module
  27. Problems with BufferedPipeOut
  28. future board design suggestions
  29. external RAM
  30. Xilinx ISE 7.1i and XEM3001.v2
  31. BufferedPipes In and Out
  32. Programming in Linux Fedora Core2
  33. programming XEM3001v2 with Borland C++
  34. About Linux Support...
  35. WriteToPipeIn() & UpdateWireIns()
  36. XEM3001v2 schematics
  37. Design for wifi and video broadcast
  38. Plea for halp
  39. Application question
  40. Use of REAL with VHDL
  41. ReadFromPipeOut XEMV1 firmware 1.5
  42. Use of provided DLL
  43. How to assign IO differential pair???
  44. Clock Rate for BufferedPipe*
  45. Bad reads from XEM module
  46. Reducing number of IOB
  47. Connecting XEM Board with PC parallel port
  48. using libusb (win32 port)
  49. 1.8V input possible
  50. Where to go from...?
  51. Can't get the "First" sample to synthesize
  52. Current (1.3.0) Driver Version?
  53. hi_busy signal
  54. Maximum data throughput
  55. okTrigoutFix XEM V1
  56. beginner question
  57. Transfer rates
  58. Pipe Timing
  59. error in doc ?
  60. Access the board from Win32 API?
  61. Visual Studio 6.0 lib for the new firmware
  62. Back to back, short transfers
  63. Extremely Large Real TIme Transfers
  64. Implementing additional buttons
  65. About the schematics?
  66. Xilinx Warnings when Building Pipetest
  67. Pipe Operation Questions
  68. Beginner-how to connect devices to XEM3001?
  69. USB problems
  70. Priority between Multiple ReadFromPipeOut
  71. Disconnecting the USB
  72. problem with downloading software
  73. problems w/ ISE 8.1i
  74. Enabling JTAG mode on startup
  75. XEM3001 version number
  76. Xilinx MicroBlaze CPU
  77. How works pipetest?
  78. oklibrary.vhd problems
  79. MicroBlaze
  80. Cy68013 Fx2?
  81. Has anyone else had this warning before?
  82. PipeIn/PipeOut fifo clocks
  83. Buffered PIPE
  84. ISE Project
  85. USB 2.0 Max Steady speed
  86. Chipscope
  87. MAX Current draw on 3.3VDD pins
  88. A strange problem with OSX, XEM, and ReadFromPipeOut
  89. Ssram
  90. ConfigureFPGA() return value?
  91. what'a the ETA on Microblaze???
  92. implementation using XFLOW, ISE 8.1i
  93. Python support on windows
  94. XEM3001 Driver Files
  95. Persistent programming
  96. tutorial 1- FPGA configuration failed
  97. Slave FIFO mode possible?
  98. XEM3001 FW not recognised
  99. New okHostInterface for FrontPanel 3.0
  100. Huge PipeTest perf with new FW !
  101. Strange problem with okWireOut and Xilinx optimization
  102. Problems with firmware v3.0
  103. SDRAM read-write problem!!!
  104. Sotware does not run on new XEM 3001.V2 boards
  105. Are 64 bit drivers available?
  106. XEM3001 V1 or V2?
  107. Where to find datasheets for the 3001?
  108. USB Packet Loss
  109. Trigger Out Question
  110. TriggerOut's trigger remain valid for too long?
  111. I/O Pin - Logical 1 and Logical 0
  112. okBTPipeOut
  113. XEM3001V1 configuration failed: Done did not go high
  114. adding configuration flash to XEM3001?
  115. Detect USB Connectivity?
  116. Changing I/O Standards
  117. Windows Vista Drivers
  118. WireIn/Out Frequency and FPGA Resource
  119. Timing Constraints
  120. PipeOut and FIFO
  121. Loss of "FrontPanel Support"
  122. Glitches on output, XEM3001v2
  123. I/O pin impedance